This application relies for priority on Korean Patent Application No. 2001-44055, filed Jul. 21, 2001, the contents of which are incorporated by this reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a ferroelectric memory device and a method of fabricating the same.
2. Description of the Related Art
A ferroelectric memory device uses a ferroelectric material such as PZT Pb(ZrxTi1x,)O3 or BST (BaSrTiO3) as a capacitor dielectric layer. The ferroelectric substance has a remnant polarization characteristic (Pr) different from a conventional dielectric substance such as oxide, silicon nitride and tantalum pentoxide. Thus, polarization is maintained even when external power is cut off and, as a result, data are retained.
Remnant polarization may be degraded during ferroelectric memory device fabrication e, g, the interconnection formation after the formation of a ferroelectric capacitor. When the interconnection is formed of a metal layer reflowed by heat treatment after deposition, the remnant polarization can be degraded by stress applied to the capacitor resulting from metal expansion. Forming the metal interconnection without reflow by thermal treatment reduces the stress and prevents degradation.
FIG. 1 is a hysteresis graph of a ferroelectric capacitor with respect to an interconnection process. The horizontal, or x-axis, shows the voltage applied to the capacitor and the vertical, or y-axis, indicates polarization per unit area of the capacitor. Line 1 is a hysteresis curve of a ferroelectric capacitor and illustrates case 1, in which the interconnection is formed of sputter-deposited aluminum, and line 2 is another hysteresis curve and illustrates case 2, in which the capacitor is made from aluminum reflowed by thermal treatment for 60 seconds at a temperature of 550xc2x0 C. after deposition.
As illustrated, case 1 has higher polarization than case 2. Even after cutting off power, the remnant polarization of case 1 is higher than that of case 2. However, when a ferroelectric memory device is fabricated using the conventional method, the sputter-deposited metal interconnection is problematic.
FIGS. 2 through 5 illustrate cross-sectional views showing a conventional method of fabricating a ferroelectric memory device.
FIG. 2 illustrates a semiconductor substrate 100 with a cell array region, xe2x80x98a,xe2x80x99 having a cell transistor and a peripheral circuit region, xe2x80x98b,xe2x80x99 having a peripheral circuit transistor. A bit line pad 112 and a storage node contact pad 114 are connected to a cell source 106 and a cell drain 104, respectively. Then, a first interlayer dielectric layer 116 is formed over the surface of the resulting structure where the bit line pad 112 and the storage node contact pad 114 are formed. A bit line 124 is connected to the bit line pad 112 through the first interlayer dielectric layer 116. Concurrently, a source/drain contact pad 126 and a gate contact pad 128 are respectively connected to a source/drain 110 and a gate electrode 108 of the peripheral circuit transistor through the first interlayer dielectric layer 116.
FIG. 3 shows the formation of a second interlayer dielectric layer 130 over the surface of the resulting structure. A storage node contact plug 138 is connected to the storage node contact pad 114 through the first and second interlayer dielectric layers 116,130. A ferroelectric capacitor 150 is then connected to the storage node contact plug 138 on the second interlayer dielectric layer 130, and a third interlayer dielectric layer 152 is formed over the surface of the substrate where the storage node contact plug 138 is formed. The second and third interlayer dielectric layers 130, 152 are sequentially patterned to form first via holes 136 exposing the source/drain contact pad 126 and the gate contact pad 128.
Referring to FIG. 4 a first conductive layer is formed over the surface of the resulting structure. As described above, the first conductive layer is formed of a sputter-deposited metal layer so as not to degrade the capacitor dielectric layer. The first conductive layer is then patterned to form a first interconnection 156 selectively connected to the source/drain node contact pad 126 and the gate contact pad 128.
The first via hole 136 has high aspect ratio because it exposes the source/drain contact pad 126 and the gate contact pad 128 through the second and third interlayer dielectric layers 130, 152. Because of the high aspect ratio, a metal layer is improperly deposited on the sidewalls of the via hole 136 and thus the first interconnection 156 is cut off or not uniformly formed as indicated at 157, thereby increasing resistance. If the first conductive layer is formed of the sputter-deposited metal layer, the problem worsens.
FIG. 5 shows a fourth interlayer dielectric layer 158 formed over the surface of the resulting structure where the first interconnection 156 is formed. The third and fourth interlayer dielectric layers 152, 158 are sequentially patterned to form a plate electrode hole 160 exposing the ferroelectric capacitor 150 and forming a second via hole 162 exposing the first interconnection 156. Next, a second conductive layer is formed over the surface of the fourth interlayer dielectric layer 158. Like the first conductive layer, the second conductive layer may be formed of a sputter-deposited metal to prevent the degradation of the ferroelectric capacitor 150. The second conductive layer is then patterned to form a plate electrode line 164 connected to the ferroelectric capacitor 150 and concurrently forms a second interconnection 166 connected to the first interconnection 156. The plate electrode line 164 and the second interconnection 166 may be selectively connected to a desired region of the semiconductor substrate-100.
As described above, in order to prevent degrading the polarization of the ferroelectric capacitor, the interconnection may be formed of sputter-deposited aluminum. However, because the metal interconnection of a conventional ferroelectric device fills the sidewalls of the high aspect ratio via hole and is connected to a gate electrode and a source/drain of the peripheral circuit, when the interconnection is formed of the sputter-deposited metal the high aspect ratio causes the metal layer to be improperly deposited on the sidewalls of the via hole. Thus, the metal interconnection is cut off and resistance is increased, degrading reliability of the metal interconnection.
It is an object of the present invention to provide a ferroelectric memory device with increased metal interconnection reliability and decreased resistance by reducing the aspect ratio of the via hole, and a method of fabricating the same.
According to one embodiment of the present invention, the device includes a semiconductor substrate having a cell array region where at least one cell transistor is arranged and a peripheral circuit region where at least one peripheral circuit transistor is arranged. Four dielectric layers are sequentially stacked over the surface of the cell array region and the peripheral circuit region. A gate contact pad and a source/drain contact pad are respectively connected to a gate electrode and a source/drain of the peripheral circuit transistor through the first interlayer dielectric layer. A gate contact plug and a source/drain contact plug are respectively connected to the gate contact pad and the source/drain contact pad, through the second interlayer dielectric layer. First via holes expose the gate contact plug and the source/drain contact plug through a third interlayer dielectric layer.
A first interconnection is arranged to extend a desired region of the semiconductor substrate between the third and fourth interlayer dielectric layers. The first interconnection may be selectively connected to the gate contact plug or the source/drain contact plug. In the ferroelectric memory device of the present invention, the first interconnection is connected to the gate contact pad and the source/drain contact pad with the gate contact plug and the source/drain contact plug respectively in the peripheral circuit region. As a result, the first via hole has a very low aspect ratio as compared with a conventional ferroelectric memory device.
According to another embodiment of the present invention, a bit line and a storage node contact pad are formed on a cell array region of a ferroelectric memory device to respectively connect with a source and a drain of the cell array region, and a first interlayer dielectric layer covers the resulting structure. A bit line is connected to the bit line pad. The bit line extends a predetermined region between the first and second interlayer dielectric layers and is connected to the bit line pad through the first interlayer dielectric layer. A ferroelectric capacitor is arranged between the second and third interlayer dielectric layers. A storage node contact plug is arranged on the storage node contact pad. The storage node contact plug is connected to the storage node contact pad and the ferroelectric capacitor through the first and second interlayer dielectric layers. A plate electrode line is arranged on the fourth interlayer dielectric layer of the ferroelectric capacitor. The plate electrode line is connected to the storage capacitor through the third and fourth interlayer dielectric layers.
According to yet another embodiment, the present invention provides a method of fabricating a ferroelectric memory device having a via hole of low aspect ratio. The method includes forming a transistor on a semiconductor substrate and then covering the transistor with a first interlayer dielectric layer; connecting a source/drain contact pad and gate contact pad with a source/drain and gate electrode of the transistor through the first interlayer dielectric layer; forming a second interlayer dielectric layer overlying the source/drain contact pad and gate contact pad; connecting a source/drain contact plug and a gate contact plug with the source/drain contact pad and the gate contact pad through the second interlayer dielectric layer; forming a third interlayer dielectric layer overlying the source/drain contact plug and the gate contact plug; patterning the third interlayer dielectric layer to form first via holes exposing the source/drain contact plug and the gate contact plug; and forming a first interconnection to extend over a predetermined region of the third interlayer dielectric layer. The first interconnection covers the sidewalls of the first via hole and is selectively connected to the source/drain contact plug and the gate contact plug.
In one aspect of the present invention, the semiconductor substrate includes a cell array region and a peripheral circuit region. At least one cell transistor is arranged in the cell array region and at least one peripheral circuit transistor is arranged in the peripheral circuit region. A bit line pad is formed on the cell source of the cell array region and a storage node contact pad is concurrently formed on a cell drain. A first interlayer dielectric layer is then formed over the bit line pad and storage node contact pad. A bit line is connected to the bit line pad. A gate contact pad and a source/drain contact pad are connected to the gate electrode and the source/drain of the peripheral circuit. A second interlayer dielectric layer is formed over the resulting structure. A storage node contact plug is connected to the storage node contact pad and a gate contact plug and source/drain contact plug are connected to the gate contact pad and source/drain contact pad. A ferroelectric capacitor is formed to be connected to the storage node contact plug on the second interlayer dielectric layer and a third interlayer dielectric layer is formed over the ferroelectric capacitor. The third interlayer dielectric layer is patterned to form first via holes exposing the gate contact plug and the source contact plug.
A first interconnection is formed to extend over a predetermined region of the third interlayer dielectric layer. The first interconnection covers the sidewalls of the first via hole and is selectively connected to the gate contact plug and the source/drain contact plug. Additionally, a fourth interlayer dielectric layer is formed over the resulting structure. A plate electrode line is formed to extend over a predetermined region of the fourth interlayer dielectric layer and to be connected to the ferroelectric capacitor through the third and fourth interlayer dielectric layers. A second interconnection is connected to the first interconnection through the fourth interlayer dielectric layer.